The present invention relates to a hybrid programmable logic device containing many programmable processors, dedicated function blocks, and programmable FPGA fabric. The present invention is particularly useful for network and packet processing, although it may be used in other applications.
Many-core (i.e., multiple core) devices have provided a way to increase performance of a device without incurring the cost of increasing clock speeds. Many-core devices may include dedicated ASIC blocks for hardware specific functions, such as error control coding or cryptography. These blocks are often referred to as hardware accelerators.